# Define SciTE settings for Verilog files.

# Verilog files
file.patterns.verilog=*.v;*.vh
filter.verilog=Verilog (verilog)|$(file.patterns.verilog)|

*filter.verilog=$(filter.verilog)

lexer.$(file.patterns.verilog)=verilog

*language.verilog=Verilog|v||

word.chars.verilog=$(chars.alpha)$(chars.numeric)_`$#
word.characters.$(file.patterns.verilog)=$(word.chars.verilog)

calltip.verilog.word.characters=$(chars.alpha)$(chars.numeric)_$

comment.block.verilog=//~
#comment.block.at.line.start.verilog=1
comment.stream.start.verilog=/*
comment.stream.end.verilog=*/
comment.box.start.verilog=/*
comment.box.middle.verilog= *
comment.box.end.verilog= */

fold.verilog.flags=0

statement.lookback.$(file.patterns.verilog)=20
statement.end.$(file.patterns.verilog)=10 ;
block.start.$(file.patterns.verilog)=5 begin case casex casez
block.end.$(file.patterns.verilog)=5 begin end endcase
statement.indent.$(file.patterns.verilog)=5 always else for if while

indent.maintain.$(file.patterns.verilog)=0

preprocessor.symbol.$(file.patterns.verilog)=`
preprocessor.start.$(file.patterns.verilog)=ifdef ifndef
preprocessor.middle.$(file.patterns.verilog)=else
preprocessor.end.$(file.patterns.verilog)=endif

keywordclass.verilog= \
always and assign automatic \
begin buf bufif0 bufif1 \
case casex casez cell cmos config \
deassign default defparam design disable \
edge else end endcase endconfig endfunction endgenerate endmodule endprimitive endspecify endtable endtask event \
for force forever fork function \
generate genvar \
highz0 highz1 \
if ifnone incdir include initial inout input instance integer \
join \
large liblist library localparam \
macromodule medium module \
nand negedge nmos nor noshowcancelled not notif0 notif1 \
or output \
parameter pmos posedge primitive pull0 pull1 pulldown pullup pulsestyle_ondetect pulsestyle_onevent \
rcmos real realtime reg release repeat rnmos rpmos rtran rtranif0 rtranif1 \
scalared showcancelled signed small specify specparam strong0 strong1 supply0 supply1 \
table task time tran tranif0 tranif1 tri tri0 tri1 triand trior trireg \
unsigned use uwire \
vectored \
wait wand weak0 weak1 while wire wor \
xnor xor

keywords.$(file.patterns.verilog)=$(keywordclass.verilog)

# Secondary keywords and identifiers
keywords2.$(file.patterns.verilog)=
keywords3.$(file.patterns.verilog)= \
$async$and$array $async$and$plane $async$nand$array $async$nand$plane $async$nor$array $async$nor$plane $async$or$array $async$or$plane \
$bitstoreal \
$countdrivers \
$display $displayb $displayh $displayo \
$dist_chi_square $dist_erlang $dist_exponential $dist_normal $dist_poisson $dist_t $dist_uniform \
$dumpall $dumpfile $dumpflush $dumplimit $dumpoff $dumpon $dumpportsall $dumpportsflush $dumpportslimit $dumpportsoff $dumpportson $dumpvars \
$fclose $fdisplayh $fdisplay $fdisplayf $fdisplayb $feof $ferror $fflush $fgetc $fgets $finish $fmonitorb $fmonitor $fmonitorf $fmonitorh $fopen $fread $fscanf $fseek $fsscanf $fstrobe $fstrobebb $fstrobef $fstrobeh $ftel $fullskew $fwriteb $fwritef $fwriteh $fwrite \
$getpattern \
$history $hold \
$incsave $input $itor \
$key \
$list $log \
$monitorb $monitorh $monitoroff $monitoron $monitor $monitoro \
$nochange $nokey $nolog \
$period $printtimescale \
$q_add $q_exam $q_full $q_initialize $q_remove \
$random $readmemb $readmemh $readmemh $realtime $realtobits $recovery $recrem $removal $reset_count $reset $reset_value $restart $rewind $rtoi \
$save $scale $scope $sdf_annotate $setup $setuphold $sformat $showscopes $showvariables $showvars $signed $skew $sreadmemb $sreadmemh $stime $stop $strobeb $strobe $strobeh $strobeo $swriteb $swriteh $swriteo $swrite $sync$and$array $sync$and$plane $sync$nand$array $sync$nand$plane $sync$nor$array $sync$nor$plane $sync$or$array $sync$or$plane \
$test$plusargs $time $timeformat $timeskew \
$ungetc $unsigned \
$value$plusargs \
$width $writeb $writeh $write $writeo
# User defined tasks and identifiers
keywords4.$(file.patterns.verilog)=
# comment keyword
keywords5.$(file.patterns.verilog)= synopsys parallel_case infer_mux TODO


# Define SciTE settings for SystemVerilog files.

# systemverilog files
file.patterns.systemverilog=*.sv;*.svh
filter.systemverilog=systemverilog (systemverilog)|$(file.patterns.systemverilog)|
lexer.$(file.patterns.systemverilog)=verilog

word.chars.systemverilog=$(chars.alpha)$(chars.numeric)_`$#
word.characters.$(file.patterns.systemverilog)=$(word.chars.systemverilog)

statement.lookback.$(file.patterns.systemverilog)=20
statement.end.$(file.patterns.systemverilog)=10 ;
block.start.$(file.patterns.systemverilog)=5 begin case casex casez
block.end.$(file.patterns.systemverilog)=5 begin end endcase
statement.indent.$(file.patterns.systemverilog)=5 always else for if while

indent.maintain.$(file.patterns.systemverilog)= 0

preprocessor.symbol.$(file.patterns.systemverilog)=`
preprocessor.start.$(file.patterns.systemverilog)=ifdef ifndef
preprocessor.middle.$(file.patterns.systemverilog)=else
preprocessor.end.$(file.patterns.systemverilog)=endif

# Taken from the SystemVerilog IEEE Std 1800-2005 Annex B
keywords.$(file.patterns.systemverilog)=\
alias always always_comb always_ff always_latch and assert assign assume \
automatic before begin bind bins binsof bit break buf bufif0 bufif1 byte case \
casex casez cell chandle class clocking cmos config const constraint context \
continue cover covergroup coverpoint cross deassign default defparam design \
disable dist do edge else end endcase endclass endclocking endconfig \
endfunction endgenerate endgroup endinterface endmodule endpackage \
endprimitive endprogram endproperty endspecify endsequence endtable endtask \
enum event expect export extends extern final first_match for force foreach \
forever fork forkjoin function generate genvar highz0 highz1 if iff ifnone \
ignore_bins illegal_bins import incdir include initial inout input inside \
instance int integer interface intersect join join_any join_none large liblist \
library local localparam logic longint macromodule matches medium modport \
module nand negedge new nmos nor noshowcancelled not notif0 notif1 null or \
output package packed parameter pmos posedge primitive priority program \
property protected pull0 pull1 pulldown pullup pulsestyle_onevent \
pulsestyle_ondetect pure rand randc randcase randsequence rcmos real realtime \
ref reg release repeat return rnmos rpmos rtran rtranif0 rtranif1 scalared \
sequence shortint shortreal showcancelled signed small solve specify specparam \
static string strong0 strong1 struct super supply0 supply1 table tagged task \
this throughout time timeprecision timeunit tran tranif0 tranif1 tri tri0 tri1 \
triand trior trireg type typedef union unique unsigned use uwire var vectored \
virtual void wait wait_order wand weak0 weak1 while wildcard wire with within \
wor xnor xor

# Secondary keywords and identifiers
keywords2.$(file.patterns.systemverilog)=

# System Tasks
keywords3.$(file.patterns.systemverilog)=\
$acos $acosh $asin $asinh $assertfailoff $assertfailon $assertkill \
$assertnonvacuouson $assertoff $asserton $assertpassoff $assertpasson \
$assertvacuousoff $async$and$array $async$and$plane $async$nand$array \
$async$nand$plane $async$nor$array $async$nor$plane $async$or$array \
$async$or$plane $atan $atan2 $atanh $bits $bitstoreal $bitstoshortreal $cast \
$ceil $changed $changed_gclk $changing_gclk $clog2 $cos $cosh $countdrivers \
$countones $coverage_control $coverage_get $coverage_get_max $coverage_merge \
$coverage_save $dimensions $display $displayb $displayh $displayo \
$dist_chi_square $dist_erlang $dist_exponential $dist_normal $dist_poisson \
$dist_t $dist_uniform $dumpall $dumpfile $dumpflush $dumplimit $dumpoff \
$dumpon $dumpports $dumpportsall $dumpportsflush $dumpportslimit $dumpportsoff \
$dumpportson $dumpvars $error $exit $exp $falling_gclk $fatal $fclose \
$fdisplay $fdisplayb $fdisplayf $fdisplayh $fdisplayo $fell $fell_gclk $feof \
$ferror $fflush $fgetc $fgets $finish $floor $fmonitor $fmonitorb $fmonitorf \
$fmonitorh $fmonitoro $fopen $fread $fscanf $fseek $fsscanf $fstrobe $fstrobeb \
$fstrobebb $fstrobef $fstrobeh $fstrobeo $ftel $ftell $fullskew $future_gclk \
$fwrite $fwriteb $fwritef $fwriteh $fwriteo $get_coverage $getpattern $high \
$history $hold $hypot $increment $incsave $info $input $isunbounded $isunknown \
$itor $key $left $list $ln $load_coverage_db $log $log10 $low $monitor \
$monitorb $monitorh $monitoro $monitoroff $monitoron $nochange $nokey $nolog \
$onehot $onehot0 $past $past_gclk $period $pow $printtimescale $q_add $q_exam \
$q_full $q_initialize $q_remove $random $readmemb $readmemh $realtime \
$realtobits $recovery $recrem $removal $reset $reset_count $reset_value \
$restart $rewind $right $rising_gclk $root $rose $rose_gclk $rtoi $sampled \
$save $scale $scope $sdf_annotate $set_coverage_db_name $setup $setuphold \
$sformat $sformatf $shortrealtobits $showscopes $showvariables $showvars \
$signed $sin $sinh $size $skew $sqrt $sreadmemb $sreadmemh $sscanf $stable \
$stable_gclk $steady_gclk $stime $stop $strobe $strobeb $strobeh $strobeo \
$swrite $swriteb $swriteh $swriteo $sync$and$array $sync$and$plane \
$sync$nand$array $sync$nand$plane $sync$nor$array $sync$nor$plane \
$sync$or$array $sync$or$plane $system $tan $tanh $test$plusargs $time \
$timeformat $timeskew $typename $ungetc $unit $unpacked_dimensions $unsigned \
$urandom $urandom_range $value$plusargs $warning $width $write $writeb $writeh \
$writememb $writememh $writeo

# User defined tasks and identifiers
keywords4.$(file.patterns.systemverilog)=
# comment keyword
keywords5.$(file.patterns.systemverilog)= synopsys parallel_case infer_mux TODO


# Verilog styles

# Default
style.verilog.32=$(font.base)
# White space
style.verilog.0=fore:#808080
# Comment
style.verilog.1=$(colour.code.comment.box),$(font.code.comment.box)
# Line Comment
style.verilog.2=$(colour.code.comment.line),$(font.code.comment.line)
# Bang comment
style.verilog.3=fore:#3F7F3F,$(font.code.comment.line),back:#E0F0FF,eolfilled
# Number
style.verilog.4=$(colour.number)
# Keyword
style.verilog.5=fore:#7f005f,bold
# Double quoted string
style.verilog.6=$(colour.string),$(font.string.literal)
# Keyword2, Secondary keywords and identifiers
style.verilog.7=fore:#007F7F
# keywords3, System tasks
style.verilog.8=fore:#804020
# Preprocessor
style.verilog.9=$(colour.preproc)
# Operators
style.verilog.10=fore:#007070
# Identifiers
style.verilog.11=
# End of line where string is not closed
style.verilog.12=fore:#000000,$(font.string.literal),back:#E0C0E0,eolfilled
# keywords4, User defined identifiers and tasks
style.verilog.19=fore:#2a00ff
# comment keyword
style.verilog.20=fore:#2A00FF
# port declare (input output ioput)
style.verilog.21=fore:#7F0000
style.verilog.22=fore:#00007F
style.verilog.23=fore:#0000FF
# port connection
style.verilog.24=fore:#005032,bold

# Turn on port styling features
lexer.verilog.portstyling=1
# Turn on treatment of all uppercase identifiers as user-defined keywords
lexer.verilog.allupperkeywords=1

# Support for colorizing inactive code due to preprocessor directives
lexer.verilog.track.preprocessor=1
lexer.verilog.update.preprocessor=1

# Inactive states are 64 greater than their active counterparts

# White space
style.verilog.64=back:#E0E0E0,eolfilled
style.verilog.65=back:#E0E0E0,eolfilled,fore:#808080,italics
style.verilog.66=back:#E0E0E0,eolfilled,fore:#808080,italics
style.verilog.67=back:#E0E0E0,eolfilled,fore:#808080,italics
style.verilog.68=back:#E0E0E0,eolfilled,fore:#808080,italics
style.verilog.69=back:#E0E0E0,eolfilled,fore:#808080,italics
style.verilog.70=back:#E0E0E0,eolfilled,fore:#808080,italics
style.verilog.71=back:#E0E0E0,eolfilled,fore:#808080,italics
style.verilog.72=back:#E0E0E0,eolfilled,fore:#808080,italics
style.verilog.73=back:#E0E0E0,eolfilled,fore:#808080,italics
style.verilog.74=back:#E0E0E0,eolfilled,fore:#808080,italics
style.verilog.75=back:#E0E0E0,eolfilled,fore:#808080,italics
style.verilog.76=back:#E0E0E0,eolfilled,fore:#808080,italics
style.verilog.83=back:#E0E0E0,eolfilled,fore:#808080,italics
style.verilog.84=back:#E0E0E0,eolfilled,fore:#808080,italics
style.verilog.85=back:#E0E0E0,eolfilled,fore:#808080,italics
style.verilog.86=back:#E0E0E0,eolfilled,fore:#808080,italics
style.verilog.87=back:#E0E0E0,eolfilled,fore:#808080,italics
style.verilog.88=back:#E0E0E0,eolfilled,fore:#808080,italics

# Braces are only matched in operator style
braces.verilog.style=10

